Open Design Computer Project





Open Design Computer Project - mist32 Processor Architecture

This Project is making a new 32-bit processor architecture “mist32”. The mist32 processor instruction sets has been optimized for Out-of-Order execution.

Our challenge is out-of-order execution processor implement as small circuit scale as possible. Out-of-Order execution is faster than in-order, however circuit scale makes bigger. Therefore, that means the processor demands more power. The mist32 instruction set architecture is reducing the dependency between instructions to make it possible.

Currently, We developed mist32 based open source processor MIST1032SA and MIST1032ISA. Those HDL code is released under 2-Clause BSD Licence.

The mist32 processor is running on FPGA (Cycrone IV - DE2-115 or Stratix III - DE3). Software toolchain for mist32 is available too. You can download GCC, GNU Binutils on Github.

Documentation in English is coming soon…

Japanese (日本語はこちら)



Out of order execution core for mist32 architecture.

  • 9-stage pipline
  • Register renaming
  • Re order buffer speculative execution
  • 120k LEs (ALTERA Cyclone IV)


In order execution core for mist32 architecture.

  • 6-stage pipline
  • 35k LEs (ALTERA Cyclone IV)

Code repository

Contact Us

  • Takahiro Ito - @cpu_labs <>
  • Hirotaka Kawata - @hktechno <hktechno at>
en/start.txt · 最終更新: 2015/06/08 11:26 by hktechno